Field effect transistor with T-shaped gate electrode

ABSTRACT

A semiconductor device with a small gate-source capacitance is fabricated by growing a semiconductor epitaxial layer of a first conductivity type on a substrate. Two metal layers that are etched at different rates are successively deposited on the epitaxial layer. The metal layers are dry-etched to form a gate electrode including a wider (larger gate length) upper gate electrode section and a narrower (smaller gate length) lower gate electrode section. The upper gate electrode section is used as a mask for implanting a dopant impurity into the semiconductor epitaxial layer to form a source region having an edge close to but not extending beneath the lower gate electrode section.

The present invention relates generally to a semiconductor device and,more particularly, to a field effect transistor with improved highfrequency characteristics and a method of fabricating such a fieldeffect transistor.

BACKGROUND OF THE INVENTION

Insulated gate field effect transistors and, more particularly,metal-oxide-semiconductor (MOS) field effect transistors arevoltage-controlled devices and have high input impedance. Because oftheir features, including the above-stated ones, which are advantageousover bipolar transistors, they are widely used as discrete devices or ICconstituent devices which are operated in low frequency regions or inhigh frequency regions.

FIG. 1 shows a cross-section of a major portion of a conventionalinsulated gate field effect transistor (IGFET) having the mostconventional structure. The IGFET 20 includes a substrate, for example,a P⁺ -type silicon (Si) substrate 10, a P-type silicon epitaxial layer11 deposited on one surface of the substrate 10, and an insulating layer12 of, for example, silicon oxide, overlying the surface of theepitaxial layer 11. The epitaxial layer 11 includes therein asource-side N-type lightly-doped-drain (hereinafter referred to as LDD)region or source region 16, and a N-type drain-side LDD region or drainregion 17 spaced from the source-side LDD region 16 by a small distancel. On that portion of the insulating layer 12 which is above the portionof the layer 11 between the regions 16 and 17 having a length l, a gateelectrode 13 is disposed. A passivation coating 18 is disposed on theinsulating layer 12 and the gate electrode 13. For reasons attributableto a manufacturing process, which will be described later, the edges ofthe two LDD regions 16 and 17 facing each other extend beyond the edgesof the gate electrode 13 into portions of the epitaxial layer 11 beneaththe gate electrode 13. Thus, the regions 16 and 17 overlap the gateelectrode 13 by lengths l₁ and l₂, respectively.

A manufacturing process for the IGFET with the above-described structureis now described with reference to FIG. 2.

First, the p⁺ -type Si substrate (not shown) is prepared. On a surfaceof the substrate, the P-type Si epitaxial layer 11 is deposited by, forexample, CVD (chemical vapor deposition). On the surface of the Siepitaxial layer 11, the insulating layer 12 is formed by, for example,thermal oxidation. A metal film 13a for the gate electrode is depositedon the layer 12 by sputtering or vapor deposition. Next, a resist isapplied over the metal film 13a, and, then, any known patterningtechnique is used to define a resist layer 14 at a location where thegate electrode is to be formed. Thus, a structure shown in FIG. 2(a)results.

Next, the resist layer 14 is used as a mask to etch the metal film 13a,which results in the gate electrode 13 having a desired length L (seeFIG. 2(b)). Thereafter, the resist layer 14 on top of the gate electrode13 is removed. Then, another resist layer 15 is deposited covering theexposed top surface of the gate electrode 13 and the exposed surface ofthe insulating layer 12. The resist layer 15 is patterned to remove thatportion on the left hand side of the center of the gate electrode 13.Next, using the remaining right hand side portion of the resist layer 15and the exposed portion of the gate electrode 13 as a mask, aconductivity determining impurity producing a conductivity type, N-typein this case, opposite to that of the epitaxial layer 11, is implantedto form the source-side LDD region 16, as shown in FIG. 2(c). Then, theresist layer 15 is completely removed, and an impurity producing thesame conductivity type (N-type) as that used for the source-side LDDregion 16 is implanted to a much lower amount (i.e. to a lowconcentration) to form the drain-side LDD 17.

Thereafter, annealing is carried out to stabilize the structure. Thedopant impurity injected in the first implantation is diffused in theepitaxial layer 11 not only in the depth direction but also in thelateral direction into a portion beneath the gate electrode 13 duringthe implantation steps and in the succeeding annealing step, and theimpurity injected in the second implantation step is diffused in theepitaxial layer 11 not only in the depth direction but also in thelateral direction into a portion of the layer 11 beneath the gateelectrode 13, during the second implantation step and the annealingstep. Thus, the overlapping portions having lengths l₁ and l₂ are formed(FIG. 2(d)).

Thereafter, a passivation coating 18 is deposited over the gateelectrode 13 and the insulating layer 12, which results in the deviceshown in FIG. 1. In both of FIGS. 1 and 2, illustration and explanationof components, such as a source electrode, a drain electrode andelectrode leads, which are not directly pertinent to the invention areomitted.

A high frequency cutoff frequency f_(T), which is one of indicesindicative of high frequency characteristics of the IGFET of theabove-described structure, is expressed as follows.

    f.sub.T =gm/2πCgs

where gm is a transconductance of the IGFET and Cgs is the gate-sourcecapacitance of the IGFET.

As is well known, the higher the high frequency cutoff frequency f_(T),the better the IGFET characteristics in high frequency regions. In theconventional structure of an IGFET shown in FIGS. 1 and 2, because theedge of the source-side LDD region 16 extends into the portion of thelayer 11 beneath the gate electrode 13, the gate-source capacitance Cgsis large. As a result, the cutoff frequency f_(T) is lowered, and thehigh frequency characteristics of the IGFET are degraded.

In order to improve the high frequency characteristics of the IGFET ofthe above-described structure, the dimensions of the gate electrode 13should be reduced as much as possible. In order to minimize thedimensions of the gate electrode 13, a highly precise masking techniquemust be employed in manufacturing the gate electrode 13. In addition,after the formation of the gate electrode 13 of such small dimensions,in order to form the source-side and drain-side LDD regions 16 and 17 bydiffusing different amounts of impurities for the respective regions, ahighly precise patterning and masking technique has to be employed todefine the edge of the resist layer 15 on the gate electrode 13 (FIG.2c). For higher operating frequencies, the dimensions of the gateelectrode 13 become smaller so that higher precision is required for thetwo masking steps, which makes the manufacturing process complicated andrequires a high degree of skill and much care. Accordingly, themanufacturing yield is significantly reduced.

Therefore an object of the present invention is to provide asemiconductor device with improved high frequency characteristics.

Another object of the present invention is to provide an insulated gatefield effect transistor which has a small gate-source capacitance and,hence, good high frequency characteristics.

Still another object of the present invention is to provide an insulatedgate field effect transistor having a significantly small gate lengthand having no overlap between a gate electrode and a source-side LDDregion so that the gate-source capacitance is very small, whichsignificantly improves high frequency characteristics.

A further object of the present invention is to provide a novel methodof fabricating a semiconductor device having improved high frequencycharacteristics.

A still further object of the present invention is to provide an improvemethod of fabricating an insulated gate field effect transistor having asmall gate-source capacitance and, hence, improved high frequencycharacteristics.

SUMMARY OF THE INVENTION

A semiconductor device of the present invention includes a semiconductorepitaxial layer having a first conductivity type, source and drainregions formed by implanting into the semiconductor epitaxial layer animpurity producing a conductivity type opposite to the firstconductivity type, and a gate electrode disposed on the semiconductorepitaxial layer with an insulating layer interposed therebetween. Thegate electrode comprises a stack of a lower gate electrode sectionhaving a smaller gate length and an upper gate electrode section havinga larger gate length. The source region is formed by implanting animpurity into the semiconductor epitaxial layer with the upper gateelectrode section being used as a mask. It is so arranged that thedrain-region-side edge of the source region does not overlap the lowergate electrode section, while it can overlap the upper gate electrodesection.

A method of manufacturing a semiconductor device according to thepresent invention includes a step of depositing an insulating layer on asurface of a semiconductor epitaxial layer which is disposed on asubstrate, a step of depositing, in the named order on the insulatinglayer, a first metallic layer which is etched at a relatively high rateby a selected etchant and a second metallic layer which is etched at arelatively low rate by the selected etchant, a step of applying a layerof first resist over said second metallic layer and patterning the firstresist layer to leave a portion of said first resist layer whichcorresponds in shape and dimension to an upper gate electrode section tobe formed, while entirely removing the remainder of said first resistlayer, a step of subjecting the stacked metallic layers and theinsulating layer to dry etching, using the remaining portion of thefirst resist layer as a mask, whereby the difference in etching ratebetween said metallic layers produces a stack of an upper gate sectionhaving a longer gate length, a lower gate section having a shorter gatelength, and the insulating layer, a step of removing the remainingportion of the first resist layer, applying, thereafter, a layer of asecond resist over the thus formed stack and the exposed surface portionof the semiconductor epitaxial layer, and then removing that portion ofthe second resist layer which is located to one side of the center ofthe upper gate electrode section (where a source region is to beformed), using the remaining portion of the second resist layer and theupper gate electrode section as a mask to implant, into thesemiconductor epitaxial layer, an impurity producing conductivity typeopposite to that of the semiconductor epitaxial layer to thereby form asource region in the epitaxial layer, and a step of removing theremaining portion of the second resist layer and implanting, into thesemiconductor epitaxial layer, an impurity producing conductivity typeopposite to that of the epitaxial layer to thereby form a drain regionin the semiconductor epitaxial layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Now, the present invention is described in detail by means of anembodiment with reference to the accompanying drawings. It should benoted that throughout the drawings the same reference numerals denotethe same or similar components or functions. In the drawings:

FIG. 1 is a cross-sectional view of a major portion of one of the mostconventional insulated gate field effect transistors;

FIGS. 2(a) through 2(d) are cross-sectional views for use in explaininga conventional method of manufacturing the insulated gate field effecttransistor shown in FIG. 1;

FIG. 3 is a cross-sectional view of a major portion of an insulated gatefield effect transistor which is an example of semiconductor devices inwhich the present invention can be embodied;

FIGS. 4(a) through 4(e) are cross-sectional views in some of successivesteps of a method, according to an embodiment of the present invention,of manufacturing the insulated gate field effect transistor shown inFIG. 3.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 3 is a cross-sectional view of a major portion of an insulated gatefield effect transistor (IGFET) 30 having improved high frequencycharacteristics, fabricated in accordance with the present invention. AnIGFET is an example of semiconductor devices in which the presentinvention can be embodied.

As shown, the IGFET 30 includes a suitable substrate, such as a P⁺ -typesilicon substrate 10. On one surface of the substrate 10, a P-typesilicon epitaxial layer 11 is disposed. An N⁺ -type source-side LDD(Lightly Doped Drain) region or source region 16 is formed in theepitaxial layer 11 adjacent the major surface thereof, and an N-typedrain-side LDD region or drain region 17 is formed also in the epitaxiallayer 11 adjacent to the major surface thereof. The source region 16 andthe drain region 17 face to each other and are mutually spaced by asmall distance l. On the surfaces of the LDD regions 16 and 17; a sourceelectrode 19a and a drain electrode 19c are disposed, respectively. Onthe surface of the portion of the epitaxial layer 11 between theelectrodes 19a and 19c (or, in other words, the surface portion of theepitaxial layer 11 between the LDD regions 16 and 17 plus some surfaceportions of the LDD regions 16 and 17), a gate insulating layer (such asa silicon oxide layer) 12 is disposed. A lower gate electrode section13a consisting of a gate electrode metal, such as molybdenum, isdisposed on the insulating layer 12 just above the portion of theepitaxial layer 11 between the two LDD regions 16 and 17. On top of thelower gate electrode section 13a, and upper gate electrode section 13bis disposed. As will be described later, the upper gate electrodesection 13b is a metallic material which is etched at a slower rate thanthe metallic material of the lower gate electrode section 13a by aselected etchant used in the manufacturing process. By purposefullyutilizing the difference in etching rates the upper gate electrodesection 13b is formed to extend laterally longer than the lower gateelectrode section 13a. A gate electrode 19b is disposed on the uppergate electrode section 13b, and a passivation film 18 overlies theentire surface of the structure. In FIG. 3, electrode leads and othercomponents which are not important to the subject of the invention arenot shown for simplicity.

Next, a method of manufacturing the IGFET 30 shown in FIG. 3, accordingto one embodiment, is described with reference to FIGS. 4(a) through4(e).

First, a substrate 10 (not shown) is prepared. A P-type siliconepitaxial layer 11 is grown on one surface of the substrate 10. As thesubstrate 10, a semiconductor substrate, an insulating substrate, asemiconductor layer disposed on an insulating member, or any othersuitable substrate well known in the semiconductor technical field maybe used. In the illustrated embodiment, a P⁺ -type silicon substrate isused. On the surface of the epitaxial layer 11 on the P⁺ -type siliconsubstrate 10, silicon oxide film 12 is disposed, from which a gateinsulating layer 12 is made. The silicon oxide film 12 may be formed by,for example, thermally oxidizing the surface portion of the siliconepitaxial layer 11. Next, molybdenum and titanium-tungsten are depositedin the named order on the silicon oxide film 12 by sputtering or vapordeposition, which results in a stack of a molybdenum film 13a' and atitanium-tungsten film 13b' on the silicon oxide film 12. A first resistis applied over the titanium-tungsten film 13b', and, by means of aphotolithographic process, a first resist layer 14 is formed at alocation where a gate electrode 13b is to be formed. This provides astructure shown in FIG. 4(a).

Next, using the first resist layer 14 as a mask, the titanium-tungstenfilm 13b', the molybdenum film 13a', and the silicon oxide film 12 aresubjected to dry etching. A halogen gas to which oxygen (O₂) or hydrogen(H₂) is added, such as Cl₂ F₂ +O₂, may be used. The metal etching rateof such an etchant gas is relatively slow for titanium-tungsten,relatively fast for molybdenum, and relatively slow for silicon oxide.Accordingly, a relatively long silicon oxide film 12, a relatively shortmolybdenum film 13a, and a relatively long titanium-tungsten film 13bare left, as shown in FIG. 4(b). The molybdenum film 13a and thetitanium-tungsten film 13b are lower and upper gate electrode sections,respectively.

Next, the first resist layer 14 shown in FIG. 4(b) is removed. A resistis again applied over this structure and, by photolithography, a secondresist layer 15 is formed, which covers the portion substantially rightof the center line of the surface of the upper gate electrode section13b and extends over the right-hand side portion of the epitaxial layer11. Another etching process is carried out, using the second photoresistlayer 15 as a mask, with the same etching gas as used in the firstetching step, namely, Cl₂ F₂ +O₂, or any other etching gas exhibiting asimilar etching characteristic. As a result of this etching, the lowergate electrode section 13a of molybdenum is side-etched from the sourceside (i.e. left-hand side of the drawing) so that the electrode-lengthmeasured in the lateral direction, i.e. the gate length L; is furtherreduced, as shown in FIG. 4(c). Thus, the lower gate electrode section13a becomes laterally shorter than the upper gate electrode section 13band, at the same time, displaced toward the drain-side LDD region (i.e.rightward) relative to the upper gate electrode section 13b.

Using the upper gate electrode section 13b and the second resist layer15 as a mask, a dopant impurity producing a conductivity type (in thiscase, N-type) opposite to the P-type epitaxial layer 11 is injected intothe epitaxial layer 11. This results in a source-side LDD region orsource region 16 (FIG. 4(c)).

Thereafter, as shown in FIG. 4(d), the second resist layer 15 isremoved, and a dopant impurity producing the same conductivity type asthe last-mentioned impurity (i.e. N-type) is injected into the epitaxiallayer in a much lower concentration than the last-mentioned impurity(low concentration implantation). This results in a drain-side LDDregion or drain region 17. After that, the structure is annealed forstabilization. In this particular embodiment, the amount of dopantimpurity injected into the epitaxial layer 11 to form the source-sideLDD region 16 is larger than the amount of dopant impurity injected toform the drain-side LDD region 17 by about two orders of magnitude.

Next, a stack of metal layers is deposited by a sequential vapordeposition of platinum and, then, gold from the above onto thestructure. Since the lower gate electrode section 13a is thinner, like amushroom stem, than the upper gate electrode section 13b, a sourcecontact 19a, a gate contact 19b, and a drain contact 19c are depositedseparately on the source-side LDD region 16, the upper gate electrodesection 13b, and the drain-side LDD region 17, respectively, in aself-aligning manner, without resort to the use of any mask. (See FIG.4(e).) Thereafter, a passivation film 18 is deposited over the entiretop surface of the structure. Thus, the IGFET with the structure shownin FIG. 3 has been completed. After that, the device is mounted on aboard, leads are connected to the device, and the device is packaged,which results in a final product.

As is understood from the description of the manufacturing method givenabove, the gate electrode of the semiconductor device of the presentinvention is formed by dry-etching the molybdenum film 13a' and thetitanium-tungsten film 13b' which are etched at different rates by aselected etching agent, and, therefore, the gate electrode has atwo-layered structure comprising the lower gate electrode section 13a ofmolybdenum having a shorter gate length and the upper gate electrodesection 13b of titanium-tungsten having a longer gate length.Furthermore, since this longer gate length upper gate electrode section13b is used as a mask (which defines a window) for forming thesource-side LDD region (i.e. source region) 16, the source region can beformed desirably to have an edge, facing the drain electrode, which doesnot extend into a portion beneath the gate electrode (more specifically,the shorter gate length lower gate electrode section 13a).

Accordingly, the thus completed semiconductor device has a gateelectrode with a short effective gate length and with no overlapping ofthe gate with the source region, so that the gate-source capacitance Cgsis greatly decreased, which results in improved high frequencycharacteristics of the device with a higher cutoff frequency f_(T).

According to the present invention, in order to provide a short gatelength, neither a mask of smaller dimensions for forming a gateelectrode, nor high precision mask registration to precisely dispose amask on a small gate electrode for forming a source region is required.Accordingly, a high manufacturing yield can be realized.

In the manufacturing process according to the present invention, beforeforming the source-side LDD region, the lower gate electrode section 13ais side-etched to make it thinner. Accordingly, better high frequencycharacteristics can be realized than conventional methods in which thegate length is determined only by mask dimensions.

According to another feature of the present invention, since the lowergate electrode section 13a is disposed between the silicon oxide film12, which is a gate insulating layer, and the upper gate electrodesection 13b, and is located significantly inward of the outer peripheryof the upper gate electrode section 13b, the use of any masks, whichwould otherwise be required for providing the source, gate and draincontacts 19a, 19b and 19c comprising low resistance metal (platinum andgold) layers, can be eliminated by sequentially evaporating platinum andgold after the and LDD regions 16, 17 are formed. This reduces the gateseries resistance to further improve the high frequency characteristicsof the device.

It should be noted that the semiconductor device and the method ofmaking it shown in FIG. 3 and FIGS. 4(a)-4(e) are only exemplary, andthe present invention is not limited to them. Various modifications canbe made to them.

For example, the conductivity types of the epitaxial layer 11, the LDDregion 16, and the LDD region 17 may be reversed from those of theillustrated embodiments to the N-type, the P-type, and the P-type,respectively.

Further, the materials of the lower and upper gate electrode sections13a and 13b are not limited to molybdenum and titanium-tungsten,respectively, but any combinations of conductive materials may be used,if they can be etched at different rates when simultaneously subjectedto dry-etching, to thereby provide the upper gate electrode section 13bwith the overhang as shown in FIG. 4(b).

As the materials for the source contact 19a, the gate contact 19b, andthe drain contact 19c, aluminum and other metals may be used, other thanplatinum and gold.

In the described manufacturing method, after the vapor deposition of thesource, gate, and drain contacts 19a, 19b and 19c, the passivationcoating 18 is deposited, but the passivation coating 18 may be depositedprior to the formation of respective contacts, which may be formed by anordinary plating technique, using electrode contact openings formed inthe coating 18 by photolithography.

In the above-described embodiment, the semiconductor body is an siliconepitaxial layer, but an epitaxial layer of a semiconductor materialother than silicon, such as an epitaxial layer of compoundsemiconductor, such as gallium arsenide (GaAs), may be used. An exampleof devices using such materials is a GaAs MISFET. Improved highfrequency characteristics as stated above can be obtained by applyingthe present invention to the gate electrode structure of MISFET's.

Further, although a high frequency transistor and a method of making ithave been described above, the present invention is also applicable toother types of semiconductor devices such as memories, to provide themwith improved high frequency characteristics.

Other various modifications may be possible within the scope of theinvention as defined by the claims.

What is claimed is:
 1. A semiconductor device comprising:a substrate; asemiconductor epitaxial layer of a first conductivity type disposed onsaid substrate; source and drain regions having a conductivity typeopposite the conductivity type of said semiconductor epitaxial layerdisposed in said semiconductor epitaxial layer and spaced from eachother; an insulating layer overlying at least a portion of saidsemiconductor epitaxial layer; and a gate electrode disposed on saidinsulating layer and comprising lower and upper gate electrode sectionshaving respective central axes perpendicular to said semiconductorepitaxial layer, said upper gate electrode section having a longer gatelength than said lower gate electrode section, said lower gate electrodesection being disposed on said insulating layer between said source anddrain regions with the central axis of said lower gate electrode sectiondisplaced closer to said drain region than the central axis of saidupper gate electrode section, said source region not extending beneathsaid lower gate electrode section in said semiconductor epitaxial layer.2. A semiconductor device according to claim 1 wherein said upper andlower gate electrode sections have respective opposed first and secondedges and the first edge of said upper gate electrode section is fartherfrom the first edge of said lower gate electrode section than the secondedge of said upper gate electrode section is from the second edge ofsaid lower gate electrode section.
 3. A semiconductor device accordingto claim 1 including a low resistance metal contact layer disposed onsaid upper gate electrode section.
 4. A semiconductor device accordingto claim 1 including a low resistance metal contact layer disposedrespectively on said upper gate electrode section, said source region,and said drain region.
 5. A semiconductor device according to claim 1wherein said lower gate electrode section is a first metallic materialand said upper gate electrode section is a second metallic materialdifferent from the first metallic material and said first metallicmaterial has a higher etching rate in an etching process than saidsecond metallic material.
 6. A semiconductor device comprising:asubstrate; a semiconductor epitaxial layer of a first conductivity typedisposed on said substrate; source and drain regions formed byimplanting a dopant impurity into said semiconductor epitaxial layer andproducing a conductivity type opposite to the first conductivity type,said source and drain regions being spaced from each other; aninsulating layer overlying at least a portion of said semiconductorepitaxial layer between said source and drain regions; and a gateelectrode disposed on said insulating layer and comprising lower andupper gate electrode sections having respective central axesperpendicular to said semiconductor epitaxial layer, said upper gateelectrode section having a longer gate length than said lower gateelectrode section, said lower gate electrode section being disposed onsaid insulating layer between said source and drain regions with thecentral axis of said lower gate electrode section displaced closer tosaid drain region than the central axis of said upper gate electrodesection, and said source region being formed by implanting a dopantimpurity in said semiconductor epitaxial layer with said upper gateelectrode section used as a mask so that said source region is locatedclose to but does not extend beneath said lower gate electrode sectionin said semiconductor epitaxial layer.
 7. A semiconductor deviceaccording to claim 6 wherein said upper and lower gate electrodesections have respective opposed first and second edges and the firstedge of said upper gate electrode section is farther from the first edgeof said lower gate electrode section than the second edge of said uppergate electrode section is from the second edge of said lower gateelectrode section.
 8. A semiconductor device according to claim 6wherein said drain region is formed by implanting a dopant impurity insaid semiconductor epitaxial layer with said upper gate electrodesection used as a mask so that said drain region is located close to butdoes not extend beneath said lower gate electrode section in saidsemiconductor epitaxial layer.
 9. A semiconductor device according toclaim 6 including a low resistance metal contact layer disposed on saidupper gate electrode section.
 10. A semiconductor device according toclaim 6 including a low resistance metal contact layer disposedrespectively on said upper gate electrode section, said source region,and said drain region.
 11. A semiconductor device according to claim 6wherein said lower gate electrode section is a first metallic materialand said upper gate electrode section is a second metallic materialdifferent from the first metallic material and said first metallicmaterial has a higher etching rate in an etching process than saidsecond metallic material.
 12. A semiconductor device comprising:asubstrate; a semiconductor epitaxial layer of a first conductivity typedisposed on said substrate; source and drain regions having aconductivity type opposite the conductivity type of said semiconductorepitaxial layer disposed in said semiconductor epitaxial layer andspaced from each other; an insulating layer overlying at least a portionof said semiconductor epitaxial layer; and a gate electrode disposed onsaid insulating layer and comprising lower and upper gate electrodesections, said upper gate electrode section having a longer gate lengththan said lower gate electrode section, said lower gate electrodesection being disposed on said insulating layer between said source anddrain regions, said upper and lower gate electrode sections havingrespective opposed first and second edges generally transverse to saidsemiconductor epitaxial layer, the first edge of said upper gateelectrode section being farther from the first edge of said lower gateelectrode section than the second edge of said upper gate electrodesection is from the second edge of said lower gate electrode section,said source region not extending beneath said lower gate electrodesection in said semiconductor epitaxial layer.
 13. A semiconductordevice according to claim 12 wherein said lower and upper gate electrodesections have respective central axes perpendicular to saidsemiconductor epitaxial layer and the central axis of said lower gateelectrode section is displaced closer to said drain region than thecentral axis of said upper gate electrode section.
 14. A semiconductordevice according to claim 12 including a low resistance metal contactlayer disposed on said upper gate electrode section.
 15. A semiconductordevice according to claim 12 including a low resistance metal contactlayer disposed respectively on said upper gate electrode section, saidsource region, and said drain region.
 16. A semiconductor deviceaccording to claim 12 wherein said lower gate electrode section is afirst metallic material and said upper gate electrode section is asecond metallic material different from the first metallic material andsaid first metallic material has a higher etching rate in an etchingprocess than said second metallic material.
 17. A semiconductor devicecomprising:a substrate; a semiconductor epitaxial layer of a firstconductivity type disposed on said substrate; source and drain regionsformed by implanting a dopant impurity into said semiconductor epitaxiallayer and producing a conductivity type opposite to the firstconductivity type, said source and drain regions being spaced from eachother; an insulating layer overlying at least a portion of saidsemiconductor epitaxial layer between said source and drain regions; anda gate electrode disposed on said insulating layer and comprising lowerand upper gate electrode sections, said upper gate electrode sectionhaving a longer gate length than said lower gate electrode section, saidlower gate electrode section being disposed on said insulating layerbetween said source and drain regions, said upper and lower gateelectrode sections having respective opposed first and second edgesgenerally transverse to said semiconductor epitaxial layer, the firstedge of said upper gate electrode section being farther from the firstedge of said lower gate electrode section than the second edge of saidupper gate electrode section is from the second edge of said lower gateelectrode section, said source region being formed by implanting adopant impurity in said semiconductor epitaxial layer with said uppergate electrode section used as a mask so that said source region islocated close to but does not extend beneath said lower gate electrodesection in said semiconductor epitaxial layer.
 18. A semiconductordevice according to claim 17 wherein said lower and upper gate electrodesections have respective central axes perpendicular to saidsemiconductor epitaxial layer and the central axis of said lower gateelectrode section is displaced closer to said drain region than thecentral axis of said upper gate electrode section.
 19. A semiconductordevice according to claim 17 wherein said drain region is formed byimplanting a dopant impurity in said semiconductor epitaxial layer withsaid upper gate electrode section used as a mask so that said drainregion is located close to but does not extend beneath said lower gateelectrode section in said semiconductor epitaxial layer.
 20. Asemiconductor device according to claim 17 including a low resistancemetal contact layer disposed on said upper gate electrode section.
 21. Asemiconductor device according to claim 17 including a low resistancemetal contact layer disposed respectively on said upper gate electrodesection, said source region, and said drain region.
 22. A semiconductordevice according to claim 17 wherein said lower gate electrode sectionis a first metallic material and said upper gate electrode section is asecond metallic material different from the first metallic material andsaid first metallic material has a higher etching rate in an etchingprocess than said second metallic material.